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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-07-20 16:34:55 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2024-08-24 14:38:31 -0500 |
| commit | ba7b9e8408ab866aa0b3c88e406b8934782402d7 (patch) | |
| tree | 0954a623e8db2cb9de58f68c83b32b1051783f36 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | arm64: dts: ti: k3-j7200-som-p0: Update mux-controller node name (diff) | |
| download | linux-ba7b9e8408ab866aa0b3c88e406b8934782402d7.tar.gz linux-ba7b9e8408ab866aa0b3c88e406b8934782402d7.zip | |
arm64: dts: ti: k3-j784s4-evm: Use 4 lanes for PCIe0 on EVM
The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4
lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM
via SERDES1. Since SERDES1 is not being used by any peripheral apart
from PCIe0, use all 4 lanes of SERDES1 for PCIe0.
Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240720110455.3043327-1-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions