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| author | Eugene Lepshy <fekz115@gmail.com> | 2024-10-14 22:48:25 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-14 18:21:35 -0500 |
| commit | f92dbc3807a92f08c5450e024e90651322ca6566 (patch) | |
| tree | bbb5cf52bfcc26504e64d05b3f52cb14f9237d29 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe (diff) | |
| download | linux-f92dbc3807a92f08c5450e024e90651322ca6566.tar.gz linux-f92dbc3807a92f08c5450e024e90651322ca6566.zip | |
arm64: dts: qcom: sc7280: Add 0x81 Adreno speed bin
A642L (speedbin 0x81) uses index 4, so this commit sets the fourth bit
for A642L supported opps.
Signed-off-by: Eugene Lepshy <fekz115@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20241014194825.44406-2-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions