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| author | Daniel Lezcano <daniel.lezcano@linaro.org> | 2025-12-08 03:08:18 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2025-12-21 11:41:12 +0000 |
| commit | a19489ca82bb5cedfe348326905fb66d66ffac65 (patch) | |
| tree | 0b93600ead6627ddbfdc78ae3f7107470fd3956d /tools/perf/scripts/python/bin/task-analyzer-record | |
| parent | 048a15b7211ada26d170b5a61248fb3356739976 (diff) | |
| download | linux-a19489ca82bb5cedfe348326905fb66d66ffac65.tar.gz linux-a19489ca82bb5cedfe348326905fb66d66ffac65.zip | |
dt-bindings: iio: adc: Add the NXP SAR ADC for s32g2/3 platforms
The s32g2 and s32g3 NXP platforms have two instances of a Successive
Approximation Register ADC. It supports the raw, trigger and scan
modes which involves the DMA. Add their descriptions.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/task-analyzer-record')
0 files changed, 0 insertions, 0 deletions