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| author | Jani Nikula <jani.nikula@intel.com> | 2025-10-10 14:07:51 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2025-10-14 12:34:58 +0300 |
| commit | dd1409b62e46bac2c46ee2fa50d2f6d2f9eb006a (patch) | |
| tree | 26bcdbec10ff8f5e350d34253d09ab85bd33771c /tools/perf/scripts/python/bin/task-analyzer-record | |
| parent | 2acee98fcc61052d63fab4539fcb6ee677555645 (diff) | |
| download | linux-dd1409b62e46bac2c46ee2fa50d2f6d2f9eb006a.tar.gz linux-dd1409b62e46bac2c46ee2fa50d2f6d2f9eb006a.zip | |
drm/i915: include gen 2 in HAS_128_BYTE_Y_TILING()
Gen 2 platforms actually have 128-byte Y-tile, it's just different from
the 128-byte Y-tile on i945+. Make the HAS_128_BYTE_Y_TILING() feature
check macro and its usage slightly less convoluted by including gen 2 in
it.
i915_tiling_ok() would strictly not need changing, but separate the if
clauses to emphasize gen 2 X-tile also being 128 bytes.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/41bf9d67a11f38f4ab0f82740f38d5c8fe0bb58b.1760094361.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/task-analyzer-record')
0 files changed, 0 insertions, 0 deletions