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| author | Thierry Bultel <thierry.bultel.yh@bp.renesas.com> | 2025-05-15 16:18:20 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-10 10:24:17 +0200 |
| commit | 065fe720eec6e627afa24da387ff970afd9a8dcb (patch) | |
| tree | 4267403fe564d5f66f7bdf048fd3b8b789ba16d3 /tools/perf/scripts/python/bin | |
| parent | Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17 (diff) | |
| download | linux-065fe720eec6e627afa24da387ff970afd9a8dcb.tar.gz linux-065fe720eec6e627afa24da387ff970afd9a8dcb.zip | |
clk: renesas: Add support for R9A09G077 SoC
RZ/T2H has 2 register blocks at different addresses.
The clock tree has configurable dividers and mux selectors.
Add these new clock types, new register layout type, and
registration code for mux and div in registration callback.
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515141828.43444-6-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions