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| author | Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> | 2024-10-28 12:30:12 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2024-10-29 07:36:34 -0700 |
| commit | 2cffe8b31068247c1acd08e6e1902280936d1d4f (patch) | |
| tree | e066a4dc240cd4c672a967ceb027965e52948a3b /tools/perf/scripts/python/bin | |
| parent | drm/i915/cx0: Remove bus reset after every c10 transaction (diff) | |
| download | linux-2cffe8b31068247c1acd08e6e1902280936d1d4f.tar.gz linux-2cffe8b31068247c1acd08e6e1902280936d1d4f.zip | |
drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register
The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD.
Bspec: 69853,69878
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-7-clinton.a.taylor@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions