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| author | Michal Wajdeczko <michal.wajdeczko@intel.com> | 2019-05-27 18:36:04 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-05-28 10:07:10 +0100 |
| commit | 4a1f9dc119163677427fe03231af3bb0bf5adb4b (patch) | |
| tree | f3832983c4b1ccb9380c34234dacc68a439c285d /tools/perf/scripts/python/bin | |
| parent | afac50928403360f481a965b9bbc97bbd06f789f (diff) | |
| download | linux-4a1f9dc119163677427fe03231af3bb0bf5adb4b.tar.gz linux-4a1f9dc119163677427fe03231af3bb0bf5adb4b.zip | |
drm/i915/guc: New GuC interrupt register for Gen11
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-9-michal.wajdeczko@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions