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| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-19 17:05:01 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-19 17:06:46 -0700 |
| commit | 4d4f9a6a192d4e580d27208e7c49dfda12cabb59 (patch) | |
| tree | c4800ee68ae2298e7fad95b82ab6576e7f79bbbc /tools/perf/scripts/python/bin | |
| parent | clk: socfpga: Fix the smplsel on Arria10 and Stratix10 (diff) | |
| parent | clk: mvebu: cp110: add sdio clock to cp-110 system controller (diff) | |
| download | linux-4d4f9a6a192d4e580d27208e7c49dfda12cabb59.tar.gz linux-4d4f9a6a192d4e580d27208e7c49dfda12cabb59.zip | |
Merge branch 'clk-cp110' of git://git.infradead.org/linux-mvebu into clk-next
Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT:
We got more information about the clock controllers and the clock tree
of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The
clk driver is modified accordingly from this new information.
* 'clk-cp110' of git://git.infradead.org/linux-mvebu:
clk: mvebu: cp110: add sdio clock to cp-110 system controller
clk: mvebu: cp110: introduce a new binding
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names
clk: mvebu: cp110: make failure labels more meaningful
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions