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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-12-06 13:13:35 +0200 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-12-11 19:20:47 +0000 |
| commit | 645fb7c22fd8d27c223b0e4abff442632bd9a75a (patch) | |
| tree | 79211fe8c6bc35307337825ad24e7328cb844e19 /tools/perf/scripts/python/bin | |
| parent | dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3S SoC (diff) | |
| download | linux-645fb7c22fd8d27c223b0e4abff442632bd9a75a.tar.gz linux-645fb7c22fd8d27c223b0e4abff442632bd9a75a.zip | |
iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S
Add ADC support for the Renesas RZ/G3S SoC. The key features of this IP
include:
- 9 channels, with one dedicated to reading the temperature reported by the
Thermal Sensor Unit (TSU)
- A different default ADCMP value, which is written to the ADM3 register.
- Different default sampling rates
- ADM3.ADSMP field is 8 bits wide
- ADINT.INTEN field is 11 bits wide
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20241206111337.726244-14-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
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