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authorRichard Zhu <hongxing.zhu@nxp.com>2025-10-15 11:04:20 +0800
committerShawn Guo <shawnguo@kernel.org>2025-11-12 09:51:28 +0800
commit798825c11e12a63b43a92b794dc157d966475b2b (patch)
treed1e3c54c841dad83e76a93bc200e9d4f512a039b /tools/perf/scripts/python/bin
parent756d0ef76e8a3ab36e05ec03e876935d526c8d37 (diff)
downloadlinux-798825c11e12a63b43a92b794dc157d966475b2b.tar.gz
linux-798825c11e12a63b43a92b794dc157d966475b2b.zip
arm64: dts: imx8mm-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8mm-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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