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| author | Petar Jovanovic <petar.jovanovic@rt-rk.com> | 2017-03-15 18:59:11 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-08-29 15:21:52 +0200 |
| commit | 846fbcfe6ffdcc86720df347e919f0389a69e6a0 (patch) | |
| tree | 1241b5943a634ee0799579797588233f07714fa1 /tools/perf/scripts/python/bin | |
| parent | MIPS: signal: Remove unreachable code from force_fcr31_sig(). (diff) | |
| download | linux-846fbcfe6ffdcc86720df347e919f0389a69e6a0.tar.gz linux-846fbcfe6ffdcc86720df347e919f0389a69e6a0.zip | |
MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1
Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and
mips64r1. This will affect show_cpuinfo() that will now correctly expose
mips32r1, mips32r2 and mips64r1 as supported ISAs.
Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com>
Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: petar.jovanovic@imgtec.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15749/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions