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| author | José Roberto de Souza <jose.souza@intel.com> | 2019-06-25 18:40:51 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-06-26 12:01:52 -0700 |
| commit | 9c811fce8a443921beaefef812c2caae8c2df427 (patch) | |
| tree | 070d9107c438585f827777dfce01112e9a23bba1 /tools/perf/scripts/python/bin | |
| parent | 092be382a2602067766f190a113514d469162456 (diff) | |
| download | linux-9c811fce8a443921beaefef812c2caae8c2df427.tar.gz linux-9c811fce8a443921beaefef812c2caae8c2df427.zip | |
drm/i915/icl: Add new supported CD clocks
Now 180, 172.8 and 192 MHz are supported.
180 and 172.8 MHz CD clocks will only be used when audio is not
enabled as state by BSpec and implemented in
intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48 MHz
but we are not reading it.
v3:
- making icl clock arrays static (Ville)
BSpec: 20598
BSpec: 15729
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190626014053.30541-1-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions