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| author | Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> | 2024-04-01 22:08:06 +0530 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2024-04-02 12:11:41 -0700 |
| commit | 9f18b55b6d3f77b9e778257efdec385d2d5dfa8e (patch) | |
| tree | 0111fdaaa59c1bd9f443c69b658f11cc80fa1b0a /tools/perf/scripts/python/bin | |
| parent | drm/xe: Normalize bo flags macros (diff) | |
| download | linux-9f18b55b6d3f77b9e778257efdec385d2d5dfa8e.tar.gz linux-9f18b55b6d3f77b9e778257efdec385d2d5dfa8e.zip | |
drm/xe/xe2: Add workaround 18033852989
This workaround applies to RCS engine's context, hence added as
LRC workaround.
v2
- Fix commit description as lrc workaround instead of engine.(Lucas)
v3
- COMMON_SLICE_CHICKEN1 is a masked register, add XE_REG_OPTION_MASKED
flag. (Matt)
BSPEC: 55899
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240401163806.3821128-1-himal.prasad.ghimiray@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions