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authorJesse Barnes <jbarnes@virtuousgeek.org>2012-06-15 11:55:13 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-06-20 14:21:23 +0200
commita0c4da24eafb32a3ce44f37b7c3412c6ffb6e37c (patch)
treeb512d984cd6e3745822640edde9fa96af8cceafd /tools/perf/scripts/python/bin
parentdrm/i915: disable flushing_list/gpu_write_list (diff)
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drm/i915: ValleyView mode setting limits and PLL functions
Add some VLV limit structures and update the PLL code. v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits v3: re-add dpio write function v4: squash in Vijay's fixes for the PLL limits and clean up the m/n finder Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/bin')
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