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| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2022-09-08 11:37:58 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-10-06 11:57:51 -0400 |
| commit | ab5220bb5a910246c61512a9e29a4e2406cb1ecd (patch) | |
| tree | a1ee7642a1fe34df800af8be08750675681daf81 /tools/perf/scripts/python/bin | |
| parent | drm/amd/display: Reorder FCLK P-state switch sequence for DCN32 (diff) | |
| download | linux-ab5220bb5a910246c61512a9e29a4e2406cb1ecd.tar.gz linux-ab5220bb5a910246c61512a9e29a4e2406cb1ecd.zip | |
drm/amd/display: fix dcn315 dml detile overestimation
DML does not take the fact that dcn315 does not have enough detile
buffer to max all pipes. This change adds a workaround to apply
the same logic DC does when calculating detile buffer size in DML.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions