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| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2014-09-02 14:19:07 -0700 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-09-16 12:55:05 +0200 |
| commit | c07c8b007732dacafd4ba9cda04ea9b9d0e8ec7d (patch) | |
| tree | 801aa2fb8603716cc196f6ba63999f3eef37584e /tools/perf/scripts/python/bin | |
| parent | ARM: zynq: PM: Enable A9 internal clock gating feature (diff) | |
| download | linux-c07c8b007732dacafd4ba9cda04ea9b9d0e8ec7d.tar.gz linux-c07c8b007732dacafd4ba9cda04ea9b9d0e8ec7d.zip | |
Documentation: devicetree: Add binding for Synopsys DDR controller
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions