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authorNeil Armstrong <neil.armstrong@linaro.org>2025-02-03 14:23:19 +0100
committerBjorn Andersson <andersson@kernel.org>2025-02-25 20:57:25 -0600
commitc516beb248a96f5a93fb4f9a6cb0dda4155eadbb (patch)
tree28e764faf029915c62318ad18fe2e160d1ef9fbf /tools/perf/scripts/python/bin
parent2250f65b32565eb8b757e89248c75977f370f498 (diff)
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arm64: dts: qcom: sm8650: harmonize all unregulated thermal trip points
While the CPUs thermal is handled by the LMH, and GPU has a passive cooldowm via the HLOS DCVS, all the other thermal blocks only have hot and critical and no passive/active trip points. Passive or active thermal management for those blocks should be either defined if somehow we can express those in DT or in the board definition if there's an active cooling device available. The tsens MAX_THRESHOLD is set to 120C on those platforms, so set the hot to 110C to leave a chance to HLOS to react and critical to 115C to avoid the monitor thermal shutdown. In the case a passive or active cooling device would be available, the downstream reference implementation uses the 95C "tj" trip point, as we already use for the gpuss thermal blocks. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250203-topic-sm8650-thermal-cpu-idle-v4-3-65e35f307301@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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