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| author | Ayaz A Siddiqui <ayaz.siddiqui@intel.com> | 2021-09-03 14:51:51 +0530 |
|---|---|---|
| committer | Ramalingam C <ramalingam.c@intel.com> | 2021-09-03 20:17:22 +0530 |
| commit | c6b248489dc3f780ee91e187a1431825d6f298fd (patch) | |
| tree | 47ded50791ec6330bf18fa70de61ac49b8b4584e /tools/perf/scripts/python/bin | |
| parent | drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward (diff) | |
| download | linux-c6b248489dc3f780ee91e187a1431825d6f298fd.tar.gz linux-c6b248489dc3f780ee91e187a1431825d6f298fd.zip | |
drm/i915/gt: Set BLIT_CCTL reg to un-cached
Blitter commands which do not have MOCS fields rely on
cacheability of BlitterCacheControlRegister which was mapped
to index 0 by default.Once we changed the MOCS value of
index 0 to L3 WB, tests like gem_linear_blits started failing
due to a change in cacheability from UC to WB.
Program and place the BlitterCacheControlRegister in
build_aux_regs().
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210903092153.535736-4-ayaz.siddiqui@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions