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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-11-20 18:41:22 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-11-28 17:44:39 +0200 |
| commit | da5bb8974c8a729aed4ce1c04fb582f13ddcb954 (patch) | |
| tree | 06136d5cda0d4a4852e3d370f272fcc96b8ba339 /tools/perf/scripts/python/bin | |
| parent | drm/i915/color: Stop using non-posted DSB writes for legacy LUT (diff) | |
| download | linux-da5bb8974c8a729aed4ce1c04fb582f13ddcb954.tar.gz linux-da5bb8974c8a729aed4ce1c04fb582f13ddcb954.zip | |
drm/i915/dsb: Nuke the MMIO->indexed register write logic
We've determined that indexed DSB writes are only faster
than MMIO writes when writing the same register ~5 or more
times. That seems very unlikely to happen in any other case
than when using indexed LUT registers. Simplify the code
by removing the MMIO->indexed write conversion logic and
just emit the instruction as an indexed write from the get go.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241120164123.12706-4-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions
