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| author | John Crispin <john@phrozen.org> | 2017-01-23 13:48:26 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-21 19:20:33 -0700 |
| commit | db9c4a1e6581e45976526eb45c032a73f944dd8a (patch) | |
| tree | dc8de0575b77860b2343ca0c6d097050cd84adc3 /tools/perf/scripts/python/bin | |
| parent | Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kern... (diff) | |
| download | linux-db9c4a1e6581e45976526eb45c032a73f944dd8a.tar.gz linux-db9c4a1e6581e45976526eb45c032a73f944dd8a.zip | |
clk: mediatek: add mt2701 ethernet reset
The ethernet clock core has a reset register that is currently not exposed
to the user. Fix this by adding the missing registration code.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions