diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2011-07-09 11:12:51 +0700 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-07-11 15:02:14 -0400 |
| commit | fe2b6afbce05abe90d31651d3b92c88e0abc5ecb (patch) | |
| tree | 3dc948acb2a9173d31d58e3a21f1ab5b02fbafbf /tools/perf/scripts/python/bin | |
| parent | ath9k_hw: initialize more timing related registers for half/quarter channels (diff) | |
| download | linux-fe2b6afbce05abe90d31651d3b92c88e0abc5ecb.tar.gz linux-fe2b6afbce05abe90d31651d3b92c88e0abc5ecb.zip | |
ath9k_hw: remove ar9287 v1.3+ specific hardcoded register hacks
Now that the clock rate is initialized properly and SIFS, EIFS, USEC,
slot time and ACK timeout are properly calculated by the generic code,
the 'async FIFO' register hacks are no longer necessary.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions