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| author | Erwan Le Ray <erwan.leray@foss.st.com> | 2021-03-04 17:23:05 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-03-10 09:34:11 +0100 |
| commit | 315e2d8a125ad77a1bc28f621162713f3e7aef48 (patch) | |
| tree | cb6fb72e2bb84a282d29d0526c7ec726815c3664 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | f16b90c2d9db3e6ac719d1946b9d335ca4ab33f3 (diff) | |
| download | linux-315e2d8a125ad77a1bc28f621162713f3e7aef48.tar.gz linux-315e2d8a125ad77a1bc28f621162713f3e7aef48.zip | |
serial: stm32: fix FIFO flush in startup and set_termios
Fifo flush set USART_RQR register by calling stm32_usart_set_bits
routine (Read/Modify/Write). USART_RQR register is a write only
register. So, read before write isn't correct / relevant to flush
the FIFOs.
Replace stm32_usart_set_bits call by writel_relaxed.
Fixes: 84872dc448fe ("serial: stm32: add RX and TX FIFO flush")
Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com>
Link: https://lore.kernel.org/r/20210304162308.8984-11-erwan.leray@foss.st.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions