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authorChris Wilson <chris@chris-wilson.co.uk>2019-12-06 10:55:23 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2019-12-06 11:39:12 +0000
commit1a74934b0effbd979c520e1122b680624a1a6372 (patch)
treefc190292e6a2568ca18b188eafcc7ed2446f402e /tools/perf/scripts/python/export-to-postgresql.py
parent045d1fb79616f138a2e51f04537acd40b9a38ce0 (diff)
downloadlinux-1a74934b0effbd979c520e1122b680624a1a6372.tar.gz
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drm/i915/gem: Flush the pwrite through the chipset before signaling
Before we signal the fence to indicate completion, ensure the pwrite through the indirect GGTT is coherent (as best as we know) in memory. Any listeners to the fence may start immediately and sample from the backing store prior to the writes being posted, thus seeing stale data. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191206105527.1130413-1-chris@chris-wilson.co.uk
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