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| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-05-04 10:08:07 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-05-16 11:08:35 -0400 |
| commit | 3290aa63ee8088b74a1e4d6ec639272a47c8e9d7 (patch) | |
| tree | 1631cafe2e3f9911f0fa950ec67f1a36565331e5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 51b8dc5163d2ff2bf04019f8bf7e3bd0e75bb654 (diff) | |
| download | linux-3290aa63ee8088b74a1e4d6ec639272a47c8e9d7.tar.gz linux-3290aa63ee8088b74a1e4d6ec639272a47c8e9d7.zip | |
media: dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings
The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to
4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on
the hardware implementation.
It can operate with an external D-PHY, an internal one or no D-PHY at all
in some configurations.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions