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| author | Matt Roper <matthew.d.roper@intel.com> | 2019-12-23 17:20:26 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2019-12-27 10:46:39 -0800 |
| commit | 4ca153827f65a6779392fff668c46f9cc54d414b (patch) | |
| tree | 12caa4d3bfd9bddfba3111ee67018618d939b6db /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl (diff) | |
| download | linux-4ca153827f65a6779392fff668c46f9cc54d414b.tar.gz linux-4ca153827f65a6779392fff668c46f9cc54d414b.zip | |
drm/i915/tgl: Extend Wa_1408615072 to tgl
Although the workaround number and description are the same, the vsunit
clock gate disable bit has moved to a new register and location on
gen12.
Bspec: 52890
Bspec: 52758
Cc: stable@kernel.vger.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-4-matthew.d.roper@intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions