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authorXiaofei Tan <tanxiaofei@huawei.com>2017-03-23 01:25:33 +0800
committerMartin K. Petersen <martin.petersen@oracle.com>2017-03-23 11:12:02 -0400
commit981843c6c4ecfa9f6bc2589e66849cde11ef820e (patch)
tree88870a863f14020b9c0c866a80a4d16067a1c35d /tools/perf/scripts/python/export-to-postgresql.py
parentscsi: hisi_sas: some modifications to v2 hw reg init values (diff)
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scsi: hisi_sas: handle PHY UP+DOWN simultaneous irq
Handle the situation that PHY UP and DOWN irq happen simultaneously. There is no mechanism of SoC HW to ensure this situation will never happen. So, we add this handle just in case. Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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