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| author | Eric Yang <Eric.Yang2@amd.com> | 2020-01-20 12:56:43 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-02-06 15:04:37 -0500 |
| commit | a39a58166901f7e72088c5eedbd17e481f0722ea (patch) | |
| tree | f791663da4cac471c663af5c5a2e93492e8d8d73 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 71b81f1275e0b5713fae86004be72719a2fa73b7 (diff) | |
| download | linux-a39a58166901f7e72088c5eedbd17e481f0722ea.tar.gz linux-a39a58166901f7e72088c5eedbd17e481f0722ea.zip | |
drm/amd/display: fix inputting clk lvl into dml for RN
[Why]
Previous logic is only good for 15W parts. Other configuration
need a smarter logic to match clk levels with pp table in the fuse.
[How]
Cache all 8 DPM level's clock data, find lvl that match each pstate
in the pp table and build input into DML base on that
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions