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| author | Mike Turquette <mturquette@linaro.org> | 2014-05-12 19:11:13 -0700 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-05-12 19:11:13 -0700 |
| commit | a854aea24c09599be75e1456f9cbe2ba78320a7b (patch) | |
| tree | 32bfeb98769bad0ed797dc0a62839fb80dee054c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: Improve clock-indices binding documentation (diff) | |
| parent | clk: socfpga: add divider registers to the main pll outputs (diff) | |
| download | linux-a854aea24c09599be75e1456f9cbe2ba78320a7b.tar.gz linux-a854aea24c09599be75e1456f9cbe2ba78320a7b.zip | |
Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga
Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions