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| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2018-01-11 16:00:07 -0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-01-19 17:57:36 -0200 |
| commit | b0d6a0f27e2ce77dc48527404d3a15ebf1b5d26d (patch) | |
| tree | b4e0a2c63a80b8c474b512f77c006f0f9bb10f2f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/icp: Get/set proper Raw clock frequency on ICP (diff) | |
| download | linux-b0d6a0f27e2ce77dc48527404d3a15ebf1b5d26d.tar.gz linux-b0d6a0f27e2ce77dc48527404d3a15ebf1b5d26d.zip | |
drm/i915/icp: Add Panel Power Sequencing Support
ICP, like BXT, has has two panel power sequencers.
v2: Simplify the code. Remove unwanted register definitions.
Make code as close to BXT style as possible. (Ville)
Also, remove the use of ICP_SECOND_PPS_BACKLIGHT for now.
Moving forward, if we are sure we need to set this register,
we can access it.
v3: Use INTEL_GEN(dev_priv), make code more readeable. (Ville)
v4 (from Paulo):
- Coding style fixes.
- Add a missing HAS_PCH_CNP -> gen10+ check.
- Rebase.
v5: Use per platform checks rather than INTEL_GEN().
v4 of this patch breaks on CoffeeLake, since CFL uses
CNP and per platform check makes sense in that case.
v6 (from Paulo):
- v5 was a patch on top of v4, not a new version. Now v6 is correctly
a new version of the original patch.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180111180010.24357-6-paulo.r.zanoni@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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