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| author | Thierry Reding <treding@nvidia.com> | 2019-12-09 13:00:04 +0100 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2020-01-15 10:49:59 +1000 |
| commit | 0d0d498265e7cb3329d2a7185b1d7cfb3be95d65 (patch) | |
| tree | 6c7b57f1c2c9e2424fe05157686d58c5917fb573 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/nouveau/secboot/gm20b,gp10b: Read WPR configuration from GPU registers (diff) | |
| download | linux-0d0d498265e7cb3329d2a7185b1d7cfb3be95d65.tar.gz linux-0d0d498265e7cb3329d2a7185b1d7cfb3be95d65.zip | |
drm/nouveau/ltc/gp10b: Add custom L2 cache implementation
There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions