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| author | Christophe JAILLET <christophe.jaillet@wanadoo.fr> | 2019-09-13 16:06:47 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-10-10 07:19:13 -0300 |
| commit | 2eca8e4c1df4864b937752c3aa2f7925114f4806 (patch) | |
| tree | 3df5ca8dbeeaafc6f6c32cd84823ec2619917ef5 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8dbdee8e8acc4f56febb8f5bf226f1ebfdd36219 (diff) | |
| download | linux-2eca8e4c1df4864b937752c3aa2f7925114f4806.tar.gz linux-2eca8e4c1df4864b937752c3aa2f7925114f4806.zip | |
media: v4l: cadence: Fix how unsued lanes are handled in 'csi2rx_start()'
The 2nd parameter of 'find_first_zero_bit()' is a number of bits, not of
bytes. So use 'csi2rx->max_lanes' instead of 'sizeof(lanes_used)'.
Fixes: 1fc3b37f34f6 ("media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions