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| author | Nicholas Piggin <npiggin@gmail.com> | 2018-05-05 03:19:28 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-06-03 20:40:26 +1000 |
| commit | 54071e4176f0cedc39809f51cdbc78edd38ee77a (patch) | |
| tree | bee09315c63fd8bcdc5c14ec844b8fdbab06099d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | powerpc/pseries: put cede MSR[EE] check under IRQ_SOFT_MASK_DEBUG (diff) | |
| download | linux-54071e4176f0cedc39809f51cdbc78edd38ee77a.tar.gz linux-54071e4176f0cedc39809f51cdbc78edd38ee77a.zip | |
powerpc/64s: micro-optimise __hard_irq_enable() for mtmsrd L=1 support
Book3S minimum supported ISA version now requires mtmsrd L=1. This
instruction does not require bits other than RI and EE to be supplied,
so __hard_irq_enable() and __hard_irq_disable() does not have to read
the kernel_msr from paca.
Interrupt entry code already relies on L=1 support.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions