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| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2025-09-24 19:45:40 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2025-09-25 18:38:19 +0530 |
| commit | 5f9172bf6f18da9c43f738b02de904d454459071 (patch) | |
| tree | 8951f16934000d5ff42793f0ac96a366c1a06834 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 94da8e5eee9c2e33cc1d2d61029c9db0c6c5a55a (diff) | |
| download | linux-5f9172bf6f18da9c43f738b02de904d454459071.tar.gz linux-5f9172bf6f18da9c43f738b02de904d454459071.zip | |
drm/i915/vrr: Clamp guardband as per hardware and timing constraints
The maximum guardband value is constrained by two factors:
- The actual vblank length minus set context latency (SCL)
- The hardware register field width:
- 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
- 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
Remove the #FIXME and clamp the guardband to the maximum allowed value.
v2:
- Use REG_FIELD_MAX(). (Ville)
- Separate out functions for intel_vrr_max_guardband(),
intel_vrr_max_vblank_guardband(). (Ville)
v3:
- Fix Typo: Add the missing adjusted_mode->crtc_vdisplay in guardband
computation. (Ville)
- Refactor intel_vrr_max_hw_guardband() and use else for consistency.
(Ville)
v4:
- Drop max_guardband from intel_vrr_max_hw_guardband(). (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (#v2)
Link: https://lore.kernel.org/r/20250924141542.3122126-9-ankit.k.nautiyal@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions