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| author | Dan Williams <dan.j.williams@intel.com> | 2022-01-31 08:44:52 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:29 -0800 |
| commit | 5ff7316f6fea4798c66b1ba953d1ebe6617503e4 (patch) | |
| tree | 864b768425ce264aa78e10a0bb194bdfe5afe283 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | cxl/core/port: Use dedicated lock for decoder target list (diff) | |
| download | linux-5ff7316f6fea4798c66b1ba953d1ebe6617503e4.tar.gz linux-5ff7316f6fea4798c66b1ba953d1ebe6617503e4.zip | |
cxl/port: Introduce cxl_port_to_pci_bus()
Add a helper for converting a PCI enumerated cxl_port into the pci_bus
that hosts its dports. For switch ports this is trivial, but for root
ports there is no generic way to go from a platform defined host bridge
device, like ACPI0016 to its corresponding pci_bus. Rather than spill
ACPI goop outside of the cxl_acpi driver, just arrange for it to
register an xarray translation from the uport device to the
corresponding pci_bus.
This is in preparation for centralizing dport enumeration in the core.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/164364745633.85488.9744017377155103992.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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