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| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2018-01-09 21:23:13 -0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-01-19 18:05:54 -0200 |
| commit | a6358dda29a2caa7967833698e690684a031f10d (patch) | |
| tree | d99f6c7119d438d8aedd769087d87cea96fdbff7 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/i915/icp: Add the ID for ICL PCH - ICP (diff) | |
| download | linux-a6358dda29a2caa7967833698e690684a031f10d.tar.gz linux-a6358dda29a2caa7967833698e690684a031f10d.zip | |
drm/i915/icl: Icelake interrupt register addresses and bits
MMIO addresses and register definition for the new interrupt
registers in Gen11.
v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter)
v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio)
v4: Bikeshedding (Paulo).
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180109232336.11029-5-paulo.r.zanoni@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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