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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-19 20:11:28 +0200 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-19 20:11:28 +0200 |
| commit | a9f57b8d5f0546bbc49448370995696ec9dcb83e (patch) | |
| tree | 1b591372adaf754865e71ace0b0395896830fd51 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clk: renesas: r9a09g047: Add I3C0 clocks and resets (diff) | |
| parent | dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID (diff) | |
| download | linux-a9f57b8d5f0546bbc49448370995696ec9dcb83e.tar.gz linux-a9f57b8d5f0546bbc49448370995696ec9dcb83e.zip | |
Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17
Renesas RZ/T2H PCLKL Clock DT Binding Definition
Peripheral Module Clock L (PCLKL) DT binding definition for the Renesas
RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions