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authorJaehyun Chung <jaehyun.chung@amd.com>2019-10-31 15:53:24 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-11-19 10:12:53 -0500
commitb9fe5151052f9d1123027e2de1e6372d884887de (patch)
tree83f2b28ce5ba3b8af17213309ecf3c502c81dae8 /tools/perf/scripts/python/export-to-sqlite.py
parent78c7738211e027f122ada3f59c2c5e8a83ee3c59 (diff)
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drm/amd/display: DML Validation Dump/Check with Logging
[Why] Need validation that we are programming the expected values (rq, ttu, dlg) from DML. This debug feature will output logs if we are programming incorrect values and may help differentiate DAL issues from HW issues. [How] Dump relevant registers for each pipe with active stream. Compare current reg values with the converted DML output. Log mismatches when found. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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