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| author | Pankaj Patil <pankaj.patil@oss.qualcomm.com> | 2025-12-11 14:32:35 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-12-16 15:23:18 -0800 |
| commit | bd0b8028ce5fbc7d9f5c2751c20661b0d8114e60 (patch) | |
| tree | c719dfaac9a95389880bac0f411cfee01afc5706 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8f0b4cce4481fb22653697cced8d0d04027cb1e8 (diff) | |
| download | linux-bd0b8028ce5fbc7d9f5c2751c20661b0d8114e60.tar.gz linux-bd0b8028ce5fbc7d9f5c2751c20661b0d8114e60.zip | |
dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
Document the Last Level Cache Controller on Glymur SoC
Glymur LLCC has 12 base register regions and an additional AND, OR
broadcast region, total 14 register regions
Increase maxItems for reg and reg-names to allow 14 entries for Glymur
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251211-glymur_llcc_enablement-v3-1-43457b354b0d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions