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| author | José Roberto de Souza <jose.souza@intel.com> | 2020-01-22 10:26:17 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-01-24 10:30:49 -0800 |
| commit | c5c772cf8d7cb68701b1c7fb9956857e646ae4b1 (patch) | |
| tree | 59f47e7cce22eef7b787bcb6882c5dc9a65ec8f7 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 58c34c4ca392ac9e658ee31f32db58abdf9fa352 (diff) | |
| download | linux-c5c772cf8d7cb68701b1c7fb9956857e646ae4b1.tar.gz linux-c5c772cf8d7cb68701b1c7fb9956857e646ae4b1.zip | |
drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed
A recent change in BSpec allow us to change EXTLINE while transcoder
is enabled so this allow us to change it even when doing the first
fastset after taking over previous hardware state set by BIOS.
BIOS don't enable PSR, so if sink supports PSR it will be enabled on
the first fastset, so moving the EXTLINE compute and set to PSR flows
allow us to simplfy a bunch of code.
This will save a lot of time in all the IGT tests that uses CRC, as
when PSR2 is enabled CRCs are not generated, so we switch to PSR1, so
the previous code would compute dc3co_exitline=0 causing a full
modeset that would shutdown pipe, enable and train link.
v2: only programming EXTLINE when DC3CO is enabled
BSpec: 49196
Cc: Imre Deak <imre.deak@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200122182617.18597-2-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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