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authorHerbert Xu <herbert@gondor.apana.org.au>2019-04-11 16:51:21 +0800
committerHerbert Xu <herbert@gondor.apana.org.au>2019-04-18 22:15:01 +0800
commitef7c5c854859d25157aae950d8112c04eb9cc96d (patch)
tree7d9cc4c17351035ff5de736b43580aaa3c828ea6 /tools/perf/scripts/python/export-to-sqlite.py
parentcrypto: sun4i-ss - Forbid 2-key 3DES in FIPS mode (diff)
downloadlinux-ef7c5c854859d25157aae950d8112c04eb9cc96d.tar.gz
linux-ef7c5c854859d25157aae950d8112c04eb9cc96d.zip
crypto: talitos - Forbid 2-key 3DES in FIPS mode
This patch forbids the use of 2-key 3DES (K1 == K3) in FIPS mode. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.3 (git 2.39.1) at 2026-02-02 23:28:19 +0000
egra is defined as well. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-23ARM: 7243/1: sp804: modernize clock event registrationLinus Walleij1-6/+1 This removes the hardcoded shift value and lets the clockevent core come up with suitable mult and div factors. Tested on the Integrator/CP. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-23ARM: 7212/1: smp_twd: reconfigure clockevents after cpufreq changeLinus Walleij1-0/+47 This break-out from Colin Cross' cpufreq-aware TWD patch will handle the case when our localtimer's clock changes with the cpu clock. A cpufreq transtion notifier will be registered only if the platform has supplied a specified clock to the TWD. After a cpufreq transition, update the clockevent's frequency by fetching the new clock rate from the clock framework and reprogram the next clock event. The necessary changes in the clockevents framework was done by Thomas Gleixner in kernel v3.0. ChangeLog v1->v2: - Replace IS_ERR_OR_NULL() with IS_ERR() in twd_clk check. - Update code to use the already existing per-cpu array of TWD clockevents instead of adding cruft. [Broke out, ifdef:ed CPUfreq stuff for non-cpufreq configs] [Rebased to newer TWD base with per-CPU clock array] Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-23ARM: 7211/1: smp_twd: get the rate from a clockLinus Walleij1-1/+39 This break-out from Colin Cross' cpufreq-aware TWD patch will optionally retrieve the clock rate of the TWD from an external clock. A variant of this patch has been proposed by Rob Herring as well. The basic idea is to avoid recalibrating the rate of the clock at boot if the platform already know what rate the clock to the TWD block has. ChangeLog v1->v2: added clk_[prepare|unprepare] calls. [Broke out of larger SMP TWD patch] Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-23ARM: 7210/1: smp_twd: modernize clock event registrationLinus Walleij1-6/+2 This break-out from Colin Cross' cpufreq-aware TWD patch will just modernize the clock event registration code to use clockevents_config_and_register(). [Broke out of larger SMP TWD patch] Signed-off-by: Colin Cross <ccross@android.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-13ARM: 7209/1: Use generic ARM instruction set condition code checks for kprobes.Leif Lindholm1-59/+7 This patch changes the kprobes implementation to use the generic ARM instruction set condition code checks, rather than a dedicated implementation. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Acked-by: Jon Medhurst <tixy@yxit.co.uk> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-13ARM: 7208/1: Add condition code checking to SWP emulation handler.Leif Lindholm1-0/+16 This patch fixes two separate issues with the SWP emulation handler: 1: Certain processors implementing ARMv7-A can (legally) take an undef exception even when the condition code would have meant that the instruction should not have been executed. 2: Opcodes with all flags set (condition code = 0xf) have been reused in recent, and not-so-recent, versions of the ARM architecture to implement unconditional extensions to the instruction set. The existing code would still have processed any undefs triggered by executing an opcode with such a value. This patch uses the new generic ARM instruction set condition code checks to implement proper handling of these situations. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-13ARM: 7207/1: Use generic ARM instruction set condition code checks for nwfpe.Leif Lindholm3-32/+5 This patch changes the nwfpe implementation to use the new generic ARM instruction set condition code checks, rather than a local implementation. It also removes the existing condition code checking, which has been used for the generic support (in kernel/opcodes.{ch}). This code has not been tested beyond building, linking and booting. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-13ARM: 7206/1: Add generic ARM instruction set condition code checks.Leif Lindholm3-1/+93 This patch breaks the ARM condition checking code out of nwfpe/fpopcode.{ch} into a standalone file for opcode operations. It also modifies the code somewhat for coding style adherence, and adds some temporary variables for increased readability. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-13ARM: 7200/1: activate TCM on the IntegratorLinus Walleij1-0/+1 Some Integrator core modules have TCM memory, so let's turn it on if it's there. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-13ARM: 7199/2: only look for TCM on ARMv5 and laterLinus Walleij1-3/+19 The Integrator AP/CP can have a varying set of core modules, some (like ARM920T) are so old that trying to read the TCM status register with CP15 will make them hang. So we need to make sure that we are running on v5 or later in order to be able to activate this for the Integrator. (The Integrator with CM926EJ-S has 32+32 kb of TCM memory.) Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-13ARM: Allow Kconfig to control the definition of NR_BANKSRussell King2-5/+6 Move the sizing of NR_BANKS to a Kconfig control instead of selecting it in a header file depending on platform selection. This allows new additions to its dependencies to be handled more gracefully. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-12-11ARM: 7202/1: Add Cortex-A7 proc infoPawel Moll1-0/+11 This patch adds processor info for ARM Ltd. Cortex-A7. A7 is architecturally identical to A15 so it shares the same SMP initialization code and hwcaps. Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>