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| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2019-07-17 19:06:22 +0100 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2019-07-19 15:35:20 +0100 |
| commit | fa380486d5f995b6914b4d4149743d330125414e (patch) | |
| tree | 863c1e656b5d3890f9630f5f7d105dde03663c88 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/i915: Fix and improve MCR selection logic (diff) | |
| download | linux-fa380486d5f995b6914b4d4149743d330125414e.tar.gz linux-fa380486d5f995b6914b4d4149743d330125414e.zip | |
drm/i915: Skip CS verification of L3 bank registers
Access to 0xb100 - 0xb3ff mmio range is controlled by the MCR selector
which only affects CPU MMIO. Therefore these registers cannot be realiably
read with MI_SRM from the command streamer so skip their verification.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717180624.20354-5-tvrtko.ursulin@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions