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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2018-11-19 14:13:57 +0100 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2018-12-17 08:26:24 +0100 |
| commit | 1970701f808095d28289c4add99a81be4ddd3790 (patch) | |
| tree | 2ca7b954bdb4baa3d7561425779d8c82e4534c31 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | mmc: renesas_sdhi: disable HS400 on H3 ES1.x and M3-W ES1.[012] (diff) | |
| download | linux-1970701f808095d28289c4add99a81be4ddd3790.tar.gz linux-1970701f808095d28289c4add99a81be4ddd3790.zip | |
mmc: tmio: introduce mask for 'always 1' bits
Some variants (namely Renesas SDHI) have bits in the STATS and IRQ_MASK
registers which are 'always 1' and should be written as such. Introduce
a seperate mask for this and apply it whenever such a register is
written.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions