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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2020-03-10 12:34:59 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-03-11 08:08:48 +0100 |
| commit | 5ca61dffc7da1ca0ac63256b5713000229dc8f1e (patch) | |
| tree | cfdaa4e9e27d81c885715be0118c243994fbc99e /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 05ffb11ca7e2c24364cb353265d6ce586fd83990 (diff) | |
| download | linux-5ca61dffc7da1ca0ac63256b5713000229dc8f1e.tar.gz linux-5ca61dffc7da1ca0ac63256b5713000229dc8f1e.zip | |
staging: mt7621-pci: enable clock bit for each port
The clock related code concerns me from the very beginning because
there are some set ups got from legacy driver that are not documented
anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1'
register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed
at all and the proper thing to do is just enable the clock bit for each
pcie port. Hence remove useless code and do the right thing which is
setting up the clock bit for each port enabled.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions