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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-24 08:56:58 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-10 10:29:26 -0700 |
| commit | 855c90d30575f95c5a1fb72f9294a9f75dae20c2 (patch) | |
| tree | 2a3b2ab05c25660230e4ce17a8d70a6ef8834b77 /tools/perf/scripts/python/flamegraph.py | |
| parent | tools/testing/cxl: Move cxl_test resources to the top of memory (diff) | |
| download | linux-855c90d30575f95c5a1fb72f9294a9f75dae20c2.tar.gz linux-855c90d30575f95c5a1fb72f9294a9f75dae20c2.zip | |
tools/testing/cxl: Expand CFMWS windows
For the x2 host-bridge interleave windows, allow for a
x8-endpoint-interleave configuration per memory-type with each device
contributing the minimum 256MB extent. Similarly, for the x1 host-bridge
interleave windows, allow for a x4-endpoint-interleave configuration per
memory-type.
Bump up the number of decoders per-port to support hosting 8 regions.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165603886721.551046.8682583835505795210.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/flamegraph.py')
0 files changed, 0 insertions, 0 deletions