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authorJonathan Marek <jonathan@marek.ca>2020-09-03 17:59:23 -0400
committerBjorn Andersson <bjorn.andersson@linaro.org>2020-09-13 23:54:50 +0000
commit9ff8b0591fcfdb455ae3797c2b592fa20a57726b (patch)
treeec0506565e3619d99b3979340bb718f4db060113 /tools/perf/scripts/python/flamegraph.py
parentarm64: dts: qcom: Add sc7180-lazor sku2 (diff)
downloadlinux-9ff8b0591fcfdb455ae3797c2b592fa20a57726b.tar.gz
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arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk
Downstream has this clock as 32000 rate, but testing shows it is close to 32768. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200903215923.14314-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/flamegraph.py')
0 files changed, 0 insertions, 0 deletions
O16 pin is gpio, when set EINT16 to IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be fixed when set its default mode as usb iddig. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2016-12-07pinctrl: bcm2835: switch to GPIOLIB_IRQCHIPLinus Walleij2-76/+65 It should be possible to use the GPIOLIB_IRQCHIP helper library with the BCM2835 driver since it is a pretty straight forward cascaded irqchip. The only difference from other drivers is that the BCM2835 has several banks for a single gpiochip, and each bank has a separate IRQ line. Instead of creating one gpiochip per bank, a single gpiochip covers all banks GPIO lines. This makes it necessary to resolve the bank ID in the IRQ handler. The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off the same gpiochip by calling gpiochip_set_chained_irqchip() repeatedly, but we have been a bit short on examples for how this should be handled in practice, so this is intended as an example of how this can be achieved. The old code did not model the chip as a chained interrupt handler, but this patch also rectifies that situation. Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Eric Anholt <eric@anholt.net> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2016-12-07pinctrl: New driver for TI DA850/OMAP-L138/AM18XX pinconfDavid Lechner3-0/+220 This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These SoCs have a separate controller for controlling pullup/pulldown groups. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>