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authorCristian Ciocaltea <cristian.ciocaltea@collabora.com>2025-10-21 13:19:14 +0300
committerHeiko Stuebner <heiko@sntech.de>2025-11-14 23:10:33 +0100
commitb0362c45c401c36412a1305b34a3bfeae35dbca7 (patch)
tree1981cc704eedf066871b42df9a58d6ad7de449a3 /tools/perf/scripts/python/libxed.py
parent836b5e9c6dbd5e5ab82d0a153483048e355a79c1 (diff)
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drm/rockchip: vop2: Check bpc before switching DCLK source
When making use of the HDMI PHY PLL as a VOP2 DCLK source, it's output rate does normally match the mode clock. But this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output rate = PHY PLL rate * 8 / bpc Hence there is no need for VOP2 to compensate for bpc when adjusting DCLK, but it is required to do so when computing its maximum operating frequency. Take color depth into consideration before deciding to switch DCLK source. Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20251021-rk3588-10bpc-v3-1-3d3eed00a6db@collabora.com
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