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| author | Mike Turquette <mturquette@linaro.org> | 2013-12-29 13:37:56 -0800 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-12-29 13:37:56 -0800 |
| commit | 6b71e0d9d6bfd24d2426a4ea7edf3c01d872903f (patch) | |
| tree | e6304ae02ad41ab2620776a7b54cdf61b1e31546 /tools/perf/scripts/python/net_dropmonitor.py | |
| parent | clk: remove CONFIG_COMMON_CLK_DEBUG (diff) | |
| parent | clk: sunxi: Allwinner A20 output clock support (diff) | |
| download | linux-6b71e0d9d6bfd24d2426a4ea7edf3c01d872903f.tar.gz linux-6b71e0d9d6bfd24d2426a4ea7edf3c01d872903f.zip | |
Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi
Allwinner sunXi SoCs clock changes
This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.
Diffstat (limited to 'tools/perf/scripts/python/net_dropmonitor.py')
0 files changed, 0 insertions, 0 deletions