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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2019-12-16 15:27:01 +0530 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-01-08 12:58:06 +0530 |
| commit | 380f57083c12936d6189fcda9e954ffcb821ec74 (patch) | |
| tree | 0d84d459a0f9423ba14f4f8a612437250107d895 /tools/perf/scripts/python/netdev-times.py | |
| parent | phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources (diff) | |
| download | linux-380f57083c12936d6189fcda9e954ffcb821ec74.tar.gz linux-380f57083c12936d6189fcda9e954ffcb821ec74.zip | |
phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers
Use "regmap" for read and write to Sierra registers. This is in
perparation for adding SERDES_16G support present in TI's J721E
SoC.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions