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| author | Zide Chen <zide.chen@intel.com> | 2025-12-31 14:42:21 -0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-01-06 16:34:24 +0100 |
| commit | 6daf2c35b835da211bf70606e9f74d1af98613a9 (patch) | |
| tree | 6dad4ec522e8d722224d4f34d50dcbee699755c9 /tools/perf/scripts/python/netdev-times.py | |
| parent | 1897336728b4ab0229fb73bb6f1e94cfe914afa9 (diff) | |
| download | linux-6daf2c35b835da211bf70606e9f74d1af98613a9.tar.gz linux-6daf2c35b835da211bf70606e9f74d1af98613a9.zip | |
perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids
DMR supports IMH PMON units for PCU, UBox, iMC, and CXL:
- PCU and UBox are same with SPR.
- iMC is similar to SPR but uses different offsets for fixed registers.
- CXL introduces a new port_enable field and changes the position of
the threshold field.
DMR also introduces additional PMON units: SCA, HAMVF, D2D_ULA, UBR,
PCIE4, CRS, CPC, ITC, OTC, CMS, and PCIE6. Among these, PCIE4 and
PCIE6 use different unit types, but share the same config register
layout, and the generic PCIe PMON events apply to both.
Additionally, ignore the broken MSE unit.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20251231224233.113839-5-zide.chen@intel.com
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions