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| author | Manasi Navare <manasi.d.navare@intel.com> | 2018-03-23 10:24:16 -0700 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-03-23 14:58:13 -0700 |
| commit | cd96bea7ba90c45c8d1d315433c78021e56ec8c7 (patch) | |
| tree | 72a7a2bb6b8cb3eacbc992bd082217959f347dc3 /tools/perf/scripts/python/netdev-times.py | |
| parent | drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI (diff) | |
| download | linux-cd96bea7ba90c45c8d1d315433c78021e56ec8c7.tar.gz linux-cd96bea7ba90c45c8d1d315433c78021e56ec8c7.zip | |
drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
This table is used for voltage swing programming sequence during DDI
Buffer initialization for MG PHY DDI Buffers on Icelake.
v2 (from Paulo):
* Fix white space issues.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180323172419.24911-5-paulo.r.zanoni@intel.com
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions